A problem in current semiconductor memory system is that the duty cycle of the input clock isn't always unchanged. The rising edge and the falling edge of the input clock may drift back and forth in time domain when memory system is read or written data, which causes data indefinite.
Referring to FIG. 1, shows a duty cycle correction circuit of prior art. The circuit comprises a duty cycle corrector 11 and a delay locked loop 15. Wherein the duty cycle corrector 11 receives an input clock (Clk_in), corrects the duty cycle of the input clock (Clk_in), and generates a correction clock (Clk_dcc). The delay locked loop 15 connected to the duty cycle corrector 11 receives the correction clock (Clk_dcc), and generates an output clock (Clk_out).
The delay locked loop 15 requires a first locking times of making the phase of the received correction clock (Clk_dcc) the same as the output clock (Clk_out).
The duty cycle corrector 11 requires a second locking times of making the phase of the received input clock (Clk_in) the same as the correction clock (Clk_dcc).
In accordance with the above prior art skill, which could be improved the drifting condition of the duty cycle. But the duty cycle correction circuit shows by FIG. 1 without the function of feed backing, therefore the delay time between the input clock and the output clock can't be tracked and reproduced.
Besides, the duty cycle correction circuit of the prior art for making the phase of the input clock (Clk_in) can equal the output clock (Clk_out). Whole circuit locking time is the sum of the first and second locking times in the case where the duty cycle corrector 11 and the delay locked loop 15 are serially connected.
The locking time is too long which is causing circuit unsteady. Drifting and phase noise still exist in the correction clock (Clk_dcc) and the output clock (Clk_out) from the duty cycle correction.